Many electronic devices, such as computers, personal digital assistants, cellular telephones, digital cameras and similar systems and devices include processors and memory. The memory is used to store computer programs to be executed by the device and/or data operated on by the processors to achieve the functionality of the device. Many devices and systems require that this information be retained in permanent storage/non-volatile medium so that the data and computer programs is not lost when power is removed.
Semiconductor memory devices that do not require ambient power to retain the data stored therein have been developed. These devices have been termed “non-volatile” semiconductor memory devices. In common designs for non-volatile semiconductor memory devices, data is erased in units of memory called sectors, and cannot be erased at the byte level. Each sector is partitioned into segments termed a page. Data is accessed for reading and programming by page, while the entire sector is accessed for erasing.
Flash memory (or Flash RAM) is an example of a non-volatile memory device. Flash memory devices use a memory cell transistor with a floating gate structure. The typical memory cell in a flash memory device comprises an access transistor and a storage element, such as a floating gate. Data in the flash memory device are programmed or erased by accumulation or depletion of charge, respectively, on a thin insulating film between a substrate and a floating gate. Programming of the memory cells occurs by applying a sufficient voltage difference to the transistors to cause excess electrons to accumulate on the floating gate. The accumulation of the additional electrons on the floating gate raises the charge on the gate and the transistor's threshold voltage. The transistor's threshold voltage is raised sufficiently above that of the applied voltage during read cycles so that the transistor does not turn on during the read cycles. Therefore, a programmed memory cell will not carry current, representing the logical value “0.” The erasure of a sector of data is caused by a process in which a voltage difference is applied to the transistor in each memory cell of the sector to cause the excess electrons on the floating gate in each transistor to evacuate the film. Thereby the transistor's threshold voltage is lowered below that of the voltage potential applied to the transistor to read data. In the erased state, current will flow through the transistor. When the read voltage potential is applied, the current will flow through the transistor of the memory cell, representing a logical value “1” stored in the memory cell.
Prior Art FIG. 1 shows a simplified diagram of an example of a non-volatile memory device which includes a plurality of memory sectors indicated by blocks SA0, SA1, SA2, . . . SA63 and SS0, SS1, SS2, . . . SS7. The memory sectors SA0, SA1, SA2, . . . SA63 and SS0, SS1, SS2, . . . SS7 are arranged in a plurality of rows and columns, with each row containing four memory sectors. The rows of the memory sectors are numbered consecutively from Z4 (0) to Z4 (17), and the columns of the memory sectors are numbered consecutively from Z3(0) to Z3(3). Sectors labeled SA0, SA1, SA2, . . . SA63 may be used for data or code storage, whereas sectors labeled SS0, SS1, SS2, . . . SS7 are reserved for code storage. Each of the sectors comprises an array of memory cells arranged in a plurality of columns and rows. A plurality of word lines are coupled to the respective rows, and a plurality of bit lines are coupled to the respective columns of the memory cells. For example, if each of the sectors labeled SA0, SA1, SA2, . . . SA63 has 64 kilobytes of memory, each sector may include an array comprising 512 word lines and 1,024 bit lines.
In one type of low voltage flash memory device the voltages required for programming and erasing must be produced by charge pumps that have a limited current capability. For example, a device may operate from an external supply voltage of 1.8 volts or 3 volts, and use an internal voltage on the order of 10 volts. For devices relying on charge pumps for erase and program voltages, the number of memory cells that can be simultaneously programmed or erased is limited.
PRIOR ART FIG. 2A shows the typical voltages applied to a memory cell when it is being programmed. The drain D of the memory cell 200 is applied a voltage on the order of about 5 V, the gate G is applied a voltage on the order of about 9 V, and the source S of the memory cell is grounded.
PRIOR ART FIG. 2B shows the typical voltages applied to the source and gate of the memory cell 200 when it is erased using a negative gate erase. The Source S of the memory cell 200 is applied a voltage on the order of about 5 V and the gate G is applied a voltage on the order of about −9 V. An alternative erase method uses a grounded gate and a positively biased source. In the context of a grounded gate, an increasing gate erase voltage refers to an increase in the of the voltage between the gate and source.
In addition to the configuration of FIG. 2B, other erase techniques such as channel erase may be employed. A discussion of channel erase may be found in U.S. Pat. No. 6,188,609, “Ramped or stepped gate channel erase for flash memory application”; the whole of which is incorporated herein by reference.
PRIOR ART FIG. 2C shows the typical voltages applied to the drain, source and gate of the memory cell 200 when it is weakly programmed. The drain D of the memory cell 200 is applied a voltage on the order of about 5 V, and the gate G and source S are grounded. Weak programming, also referred to as Automatic Program Disturb after Erase (APDE), is a self-limiting correction that may be applied to over-erased memory cells.
In order to program a 16-bit word, for example, sixteen columns of memory cells on sixteen bit lines are grouped into four sets, each set comprising four columns. When the memory cells are programmed in a conventional embedded program mode, the conventional internal pump provides pump currents through the respective bit lines to program the memory cells one set of columns at a time. For example, a typical 16-bit word with bits numbered 0-15 may be grouped into four sets of bits numbered 0-3, 4-7, 8-11 and 12-15. When any set of four bits are to be programmed with up to four zeroes, this arrangement ensures that a sufficient pump current is supplied to the drain of each of the memory cells through the respective bit line. When the memory cells are in a conventional embedded chip erase mode, the conventional internal pump has similar limitations in that it is capable of erasing the memory cells by supplying a source voltage to the sources of only one set of memory cells at a time.
Because the conventional internal pump has a limited current supply and is typically capable of programming or erasing the memory cells on the bit lines only one set at a time, it takes a plurality of pulses generated by the internal pump to be supplied to different sets of bit lines during the programming or erase of each word along each word line. Moreover, the power from the internal pump need be switched to different sets of bit lines during the programming or erase of each word. Therefore, programming and erasing of a whole sector of memory cells can be time consuming in the conventional embedded program and erase modes.
In another type of flash memory device, the internal limitations of charge pumps is circumvented by allowing the optional input of an additional higher voltage that can be selected in place of the internal voltage generated by a charge pump. This type of device allows for faster programming and erasing due to the greater current capability. The optional high voltage input provides the capability for delivering an erase pulse to multiple sectors simultaneously. An erase pulse is essentially a voltage applied for a period of time. However, although the number of sectors to which an erase pulse can be applied has been increased, the basic process for applying pulses has remained largely the same as that used to erase a single sector.
In the typical single sector erase process, the erase voltage may be sequentially increased in order to maintain accurate control over the erase/verify process. After a sector has been erased and verified, the erase voltage is reset to an initial value. In multiple sector erase, the erase pulses are applied to a plurality of sectors, and the sectors are verified individually. After an individual sector has been verified, it is possible that one or more of the remaining sectors may require additional pulses. Although there is no harm in resetting the erase voltage after verifying a single sector, any subsequent pulses that are required for the remaining sectors will begin with the reset voltage, which will usually be less than the voltage previously applied. After reset, a number of pulses will be required to achieve an actual increase in applied voltage for the remaining sectors. The extra pulses that are required result in longer overall erase times. Thus, a need exists for an erase voltage control method that provides a reset that does not require an increase in the number of pulses applied during multiple sector erase.